Calculating Kill Ratios on Multi-Component Devices
The advent of multi-component devices has served to slow the reduction in die size. Relying on die-level contingency analysis to determine kill ratios for ever shrinking design rules is no longer adequate. A means of utilizing the data from die components is necessary in order to preserve kill ratio accuracy. The application of a yield model is presented as a means of utilizing component-level data for kill ratio calculation.
Key words — kill ratio, multi component, negative binomial, D0
The progress to multi-component architectures in high end microprocessors and graphic processors has been well under way for the past decade. Leading edge microprocessors are now very heterogeneous in nature; containing a wide range of discrete component types (e.g. NorthBridge, PCIe, Display Port).
More recently this trend has also appeared in general purpose microprocessors and even microcontrollers. This indicates that a method of calculating kill ratios and loss estimates for manufacturing defects which utilizes the discrete component results should now be more generally applicable, when attempting to quantify the defect generated yield loss per wafer inspection step.
2. The Challenge
The primary difficulty with utilizing component-level SORT data when calculating kill ratios are those die affected by a gross defect or a peripheral defect, both of which can result in the loss of component-level data.
Fig. 1: Example of three die with a defect generated die-level fail on the middle die.
In the case of the examples shown in Fig.1 the components of the middle die cannot be treated independently, but rather need to be considered as a single die-level failure.
In order to illustrate the issues associated with die-level fails, consider the synthesized wafer maps in Fig. 2. The yield difference between the Defective Die (Yd) and Non-Defective Die (Yc) is traditionally used to calculate the kill ratio according to equation (1). This results in a kill ratio estimate of 9.2%. Performing the same calculation at the component-level but treating die-level fails as single elements, results in a kill ratio estimate of 17.4%.
KR = 1-(Yd ⁄ Yc) (1)
Fig.2: Artificially generated wafer maps showing (a) a Defect Density Map and SORT Maps highlighting (b) the defective die and © defective components plus defective die-level fails.
The accuracy and selectivity of the die-level correlation is clearly under suspicion because of the relatively large die size. However, the component-level calculation is also questionable because the defective components include a higher proportion of die-level fails (Fig. 2c). The larger area of the die-level fails naturally have a higher probability of being defective than a true component and hence adversely influencing the Kill Ratio. This higher probability needs to be factored into the component-level yield values, prior to calculating a component-level kill ratio.
3. The Impact of Component Area on Defectivity
Fig.3: Probability of die or components being defective vs. Defects/Wafer
Examining the difference in the probability of die elements being defective for typical die and component sizes, over the range of wafer defectivity values, produces the response shown in Figure 3. Unsurprisingly, at low defectivity levels (i.e. < 20 defects/wafer) the difference in the probability of being defective between a die and component is low and would only marginally affect the kill ratios. Beyond this defectivity level the difference in the probability becomes unacceptable as it will increasingly put any die-level fails into the defective category, thus erroneously increasing the kill ratio.
4. A Solution — Area Correction
One method of resolving this issue is to use a yield model to translate the yield values for the defective and non-defective components to the equivalent yield for die elements of the size of a typical Component. This yield conversion is performed according to equation (2), which is derived from the negative binomial equation as first proposed by Okabe, et al , Stapper  and later comprehensively validated by Stapper, et al .
These calculations are performed for the defective and non-defective die elements at every wafer-step, where the clustering factor (α) as defined by equation (3) is obtained from the inspection scan where λ and σ² are the mean and variance for the number of defects per die, as described by Cunningham . The actual component area is represented by Ac and the average area and yield of the wafer elements under investigation are represented by Ai and Yi, respectively.
Yo=(1+(Ac/Ai)* (Yi^(-1⁄α)-1))^-α (2)
α= λ/(σ²- λ ) (3)
Table.1: Defective and non-defective yields before (Yi) and after (Yo) area correction
Applying equation (2) to the example wafer results in the yield conversions as shown in table 1. The area corrected yields result in a kill ratio of 4.6%. This is in line with the expected value for the primary defect mechanism at the inspection step in question and indicates that the area-correction method does allow the component-level data to be utilized as a more precise assessment of kill ratios, for individual wafer inspection steps.
5. Calculating Loss from Component-Level Kill Ratios
Estimating the number of die lost from the component-level kill ratio requires a different treatment than that normally used by the die-level calculation. The method utilized is the same as that to estimate loss for die with a given number of defects where the kill potential per defect is known. In this case, instead of defects the number of defective components per die is used. The number of lost die is given by equation (4).
Die Loss=∑(i=1->n) Di -(Di*(1-Kc)^i) (4)
Kc=Component-Level kill ratio
i=number of defective components per die
Di=number of die with i defective components
Special consideration need to be given for defect signatures which show a high degree of selectivity for complete die-level fails (i.e. high defect kill potential, Kc > 80%) and which have no clustering (i.e. Clustering Factor > 10). In such cases, the average area of the defective units approaches that of the die area and the absence of any clustering means that no kill ratio scaling occurs because there are relatively few defective components per die. This results in the component-level loss estimate that significantly underestimates the loss which is accurately estimated by the die-level calculation. The die-level loss estimate should be used when these characteristics are observed.
6. Component-Type Specific Kill Ratios
Naturally, once the data for all components have been combined to produce an overall kill ratio for a wafer inspection step, the question arises as to what are the kill ratios for the individual component types and do they display differing yield responses. Displaying the yield response versus the number of defects per component is best visualized by translating the yields into D0 values.
The shaded blue areas in Figure 4 depict the expected response of the largest component type (i.e. the A-Type component), if the yield relationship between the non-defective A-Type components and those with a single defect, is maintained over an extended range of defect density.
A monotonic response indicates a clear yield impact attributable to the relevant defects and lends certainty to the modeled kill ratio. The average component-level kill ratio for all component types should normally be within a range defined by the largest component type, from the kill ratio for components with a single defect to the average value for all A-Type components. Any unexplained divergence would indicate the presence of an atypical failure mechanism.
Fig.4: Visualization of specific component-type’s yield response vs. the number of defects per component (a) including A-Type component redundancy repair [2.7% per defect, rising to 12.9% for all A-Types ] and (b) excluding redundancy [12.7% per defect, rising to 29.1% for all A-Types].
The application of the negative binomial model has been demonstrated to allow component-level SORT data to be utilized for more precise kill ratio calculation and subsequently yield loss assessment, when quantifying the defect assignable loss on a wafer inspection step basis.
Plotting of D0 for each component type versus the number of defects per component can illustrate differences in the response of different component types to increasing defectivity for specific wafer inspections scans and serve to increase the confidence in the aggregated component-level kill ratios.
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